DRAM
1 transistor + 1 capacitor per memory cell
High density
Slow access latency of 50-70ns
Memory wall
1 GHz Processor -> 1 ns per clock cycle
50 ns for DRAM access -> 50 processor clock cycles per memory access
1 transistor + 1 capacitor per memory cell
High density
Slow access latency of 50-70ns
1 GHz Processor -> 1 ns per clock cycle
50 ns for DRAM access -> 50 processor clock cycles per memory access