# disjoint memory mapping

Mapping is done with page tables and translation look-aside buffers (TLBs).

Page table are a software solution (implemented within process PCBs). When referencing memory, we have to perform table look up (1 memory access), access the actual address (total: 2 memory access). This is twice the expected time.

To augment this, we have (TLBs). This is a cache which maps logical page frames to physical page frames.

## The effectiveness of TLBs

Suppose TLBs have a latency of 1ns access, and main mem have 50ns access. If they work 90% of the time (cache hit 90%):

cache hit time taken, T_hit = TLB access + mem access = 1 + 50
cache hit time taken, T_miss = TLB access + page access + mem access = 1 + 50 + 50
time taken to reference mem = 0.9 * T_hit + 0.1 * T_miss = 56ns

This is roughly equivalent to direct access!

Note that we can avoid overhead from filing TLB cache (hardware can hide away this cost)

## An aside on TLBs’ shortcomings

TLBs are rather small and belong to a processes’ hardware context. This means when there’s context switch, the TLB gets cleared, and when initializing, there will be cache misses.