MIPS instruction pipelining
Break up instructions into execution steps:
1 per clock cycle.
Allow instructions to be in different execution steps simultaneously.
- IF -
- ID - +
- EX -
- MEM -
- WB -
Each execution stage takes 1 clock cycle
Generally from one stage to next.
Update of PC -
Write back of register file (WB)
State used by subsequent instructions
Store in programmer-visible state elements: PC, register file & memory.
State used by same instruction
We use additional registers to manage these. ()
We still require some way to manage.