MIPS instruction pipelining
Break up instructions into execution steps: 1 per clock cycle.
Allow instructions to be in different execution steps simultaneously.
Execution stages
- IF - MIPS Instruction fetch / IF Stage
- ID - MIPS Instruction Decode / ID Stage + MIPS operand fetch / ID Stage
- EX - MIPS Arithmetic-logical unit (ALU) / EX Stage
- MEM - MIPS memory access / MEM Stage
- WB - MIPS result write / WB Stage
Each execution stage takes 1 clock cycle
Data flow
Generally from one stage to next.
Exceptions
Update of PC - How does MIPS handle the program counter (PC)?
Write back of register file (WB)
Optimization
Managing state
State used by subsequent instructions
Store in programmer-visible state elements: PC, register file & memory.
State used by same instruction
We use additional registers to manage these. (MIPS pipeline registers)
Pipeline control
We still require some way to manage MIPS Processor Control, control signals .
