MIPS instruction pipelining

Break up instructions into execution steps: 1 per clock cycle.

Allow instructions to be in different execution steps simultaneously.

Execution stages

  1. IF - MIPS Instruction fetch / IF Stage
  2. ID - MIPS Instruction Decode / ID Stage + MIPS operand fetch / ID Stage
  3. EX - MIPS Arithmetic-logical unit (ALU) / EX Stage
  4. MEM - MIPS memory access / MEM Stage
  5. WB - MIPS result write / WB Stage

Each execution stage takes 1 clock cycle

Data flow

Generally from one stage to next.



Managing state

State used by subsequent instructions

Store in programmer-visible state elements: PC, register file & memory.

State used by same instruction

We use additional registers to manage these. (MIPS pipeline registers)

Pipeline control

We still require some way to manage MIPS Processor Control, control signals .

MIPS pipeline control signals


MIPS pipelining performance